1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which a desired circuit is formed by arranging a plurality of circuit cells (for example standard cells) including a transistor having a gate electrode in combination with each other and interconnecting the cells by a metallic wiring layer.
2. Description of the Related Art
Because progress has been made in miniaturization of semiconductor LSIs (Large Scale Integrations), a ratio between delay within a logic circuit element (which delay will hereinafter be referred to as a “gate delay”) and wiring delay is changing greatly.
A past LSI that did not advanced so much in miniaturization had a high ratio of gate delay to wiring delay among elements accounting for signal delays of the whole LSI or a whole circuit block. Thus, in estimating the delay of a whole signal path in a stage of logic synthesis of LSI design, a total amount of delay did not greatly deviate from a prediction unless there is an error in estimating each gate delay.
Progress made in miniaturization in recent semiconductor processes has increased a ratio of wiring delay to a total signal delay. It is therefore important to estimate wiring delay correctly.
However, in the stage of logic synthesis, a state of wiring layout is not known, and thus wiring delay cannot be determined and is difficult to estimate. It is therefore difficult to estimate timing of operation in a whole signal path.
For example, unless an amount of delay in a circuit part up to a preceding stage connected to each of a plurality of inputs of a certain gate circuit can be estimated with a certain degree of accuracy, it is not possible to estimate timing in consideration of the delay of each input with respect to the operation of the gate circuit and a tolerable amount of delay (delay margin). Estimations of timing in such individual gate circuits are totaled, and timing design is made for correct operation in a whole signal path. However, uncertainty of wiring delay introduces a large error into estimation of timing in the whole signal path.
Thus, a path delay time estimated by a logic synthesis tool and a path delay time in an actually completed LSI deviate from each other, and erroneous operation, that is, erroneous logical inversion tends to occur. A difficulty in securing a noise margin due to the lowering of voltage also spurs an increase in frequency of erroneous logical inversion.
In addition, the miniaturization of semiconductor elements has enabled the incorporation of more logic gate circuits, complicated logic, and increased the frequency of logical errors.
For such reasons, ECOs (Engineering Change Orders: requests for a circuit change after design) from a client requesting design are expected to increase before or after completion of the design or at a time of sample evaluation.
As a method for dealing with an ECO at a low cost and in a short time, a method of embedding reserve cells for circuit change after design in unused parts of a standard cell arrangement region is known (see for example Japanese Patent Laid-Open No. 2006-269900).
A reserve cell will hereinafter be referred to as an “ECO cell” or an “ECO filler.” In addition, such a design method will hereinafter be referred to as an “ECO cell aided design.”